| Design Intent Capture |
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CoverAll™ is a comprehensive suite of utilities which capture design intent and automatically generates assertions and functional cover properties for use in formal and simulation based verification flows.
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| CoverAll™ converts design intent captured in easy to construct flow, state and timing diagrams and automatically creates assertion based properties: |
 Logic Assertions - each state in the flow diagram generates an assertion property |
| Path Covers - the path(s) to each state are captured with functional coverage points |
FSMs - creates assertion properties for state transitions, holding terms and feedback paths. In addition, CoverAll™ creates sequences for all paths originating from the reset state. |
Timing Diagrams - creates sequences for each clock and assertion properties between signal on the diagram |
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| CoverAll™ |
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Flow Chart to Assertions
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The Flow Chart to Assertions module, FC2Assert, is a Microsoft Visio add-on which automatically converts functional flow diagrams drawn with the provided stencil into assertions and path covers. Sequence assertions are also extracted from flow diagrams created with multiple states for constructs such as state machines or pipelined logic. In addition, the Enterprise version of FC2Assert can read legacy Verilog or System Verilog RTL, convert the design into flow diagrams and automatically generate the assertions, path covers, and state sequences. |
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Timing Diagram to Assertions
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The Timing Diagram to Assertions module, TD2Assert, is a Microsoft Visio add-on which converts timing diagrams drawn with the provided stencil into coverage assertions and sequences. In addition, the Enterprise version of TD2Assert can read and convert an EVCD Waveform file output from commercially available simulation tools.
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| Verilog to Flow Charts |
The Verilog to Flow Charts module, Ver2FC, converts legacy and Intellectual Property (IP) RTL verilog into flow diagrams. These diagrams can then be processed by the FC2Assert module to automatically generate assertions, path covers, and state sequences.
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| VCD to Timing Diagrams |
The VCD to Timing Diagram module, VCD2TD, converts simulation waveforms captured in VCD or eVCD format into flow diagrams. These diagrams can then be processed by the TD2Assert module to automatically generate assertions and sequences.
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| The CoverAll™ Library |
The CoverAll™ Library is a collection of common structures, such as counters, muxes, registers and state diagram macros which speed the creation of the Design Intent flow diagrams.
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| BindAll™ |
The BindAll™ product takes the assertion files created by the CoverAll™ Compiler and the design Verilog RTL and automatically creates bind modules for use in Simulation and Formal Verification. BindAll™ can also create a simple testbench environment and script files for commercially available formal verification software. BindAll™ currently supports Synopsys Magellan™ Hybrid Formal Verification and Mentor Graphics 0in Formal Verification products.
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All tools support the PSL and SVA assertion languages and the Open Verification Library(OVL). |
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