Spec + RTL + Coverage = Success

I recently listened in on a Webcast where the Wilson Research Group and Mentor Graphics 2012 Functional Verification Study was presented. You can read about it here. The slides show that the percentage of non-FPGA respins caused by logic or functional flaws was ≈55% in 2004 and ≈48% in 2012. That’s only a 7% improvement in 8 years! They also show that only 25% of development teams are using functional coverage as sign-off criteria. Why such a meager following? Continue reading