If you research Assertion Based Verification (ABV), you’ll run into the terms “observability” and “controllability” a lot. Observability means assertions detect design errors at their source, at the instant the error occurs which ultimately decreases debug time.
Low controllability occurs when the number of simulation vectors needed to exhaustively stimulate a design becomes prohibitive. Assertions, when utilized as targets for formal analysis, can provide exhaustive verification of blocks and interfaces and improve controllability. Continue reading