If you research Assertion Based Verification (ABV), you’ll run into the terms “observability” and “controllability” a lot. Observability means assertions detect design errors at their source, at the instant the error occurs which ultimately decreases debug time.
Low controllability occurs when the number of simulation vectors needed to exhaustively stimulate a design becomes prohibitive. Assertions, when utilized as targets for formal analysis, can provide exhaustive verification of blocks and interfaces and improve controllability. Continue reading
I recently listened in on a Webcast where the Wilson Research Group and Mentor Graphics 2012 Functional Verification Study was presented. You can read about it here. The slides show that the percentage of non-FPGA respins caused by logic or functional flaws was ≈55% in 2004 and ≈48% in 2012. That’s only a 7% improvement in 8 years! They also show that only 25% of development teams are using functional coverage as sign-off criteria. Why such a meager following? Continue reading
I recently read a couple of items on Assertion Synthesis. It got me thinking about how Assertion-based verification is utilized in the design/verification community and what is the best approach to an effective first silicon success methodology which utilizes ABV. Continue reading
Don’t get me wrong, I still create RTL, I just don’t “write it” anymore. OK, most of it anyway. I stopped “writing it” because I can’t hide from verification engineers.